80C554 Datasheet, PDF (64/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
DC ELECTRICAL CHARACTERISTICS (Continued)
V_DD and T_amb minimum and maximum, per device specifications table.
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs (Continued)
AV_IN
Analog input voltage
AV_SS–0.2 AV_DD+0.2
V
AV_REF
Reference voltage:
AV_REF–
AV_REF+
AV_SS–0.2
V
AV_DD+0.2
V
R_REF
Resistance between AV_REF+ and AV_REF–
10
50
kΩ
C_IA
Analog input capacitance
15
pF
t_ADS
Sampling time (10 bit mode)
8t_CY
µs
t_ADS8
Sampling time (8 bit mode)
5t_CY
µs
t_ADC
Conversion time (including sampling time, 10 bit mode)
50t_CY
µs
t_ADC8
Conversion time (including sampling time, 8 bit mode)
24t_CY
µs
DL_e
Differential non-linearity^{10, 11, 12}
IL_e
Integral non-linearity^{10, 13} (10 bit mode)
±1
LSB
±2
LSB
IL_e8
Integral non-linearity (8 bit mode)
±1
LSB
OS_e
Offset error^{10, 14} (10 bit mode)
±2
LSB
OS_e8
Offset error (8 bit mode)
±1
LSB
G_e
Gain error^{10, 15}
±0.4
%
A_e
Absolute voltage error^{10, 16}
±3
LSB
M_CTC
Channel to channel matching
±1
LSB
C_t
Crosstalk between inputs of port 5^{17, 18}
0–100 kHz
–60
dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 57 through 61 for I_DD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10 ns; V_IL = V_SS + 0.5 V;
V_IH = V_DD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V_DD; STADC = V_SS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10 ns; V_IL = V_SS + 0.5 V;
V_IH = V_DD – 0.5 V; XTAL2 not connected; Port 0 = EW = V_DD; EA = RST = STADC = V_SS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V_DD;
EA = RST = STADC = XTAL1 = V_SS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I²C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V_IN is approximately 2 V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0.9 V_DD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: V_DD – 0.2 V < AV_DD < V_DD + 0.2 V.
10. Conditions: AV_REF– = 0 V; AV_DD = 5.0 V. Measurement by continuous conversion of AV_IN = –20 mV to 5.12 V in steps of 0.5 mV, deriving
parameters from collected conversion results of ADC. AV_REF+ (87C554) = 5.12 V. ADC is monotonic with no missing codes.
11. The differential non-linearity (DL_e) is the difference between the actual step width and the ideal step width. (See Figure 48.)
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL_e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 48.)
14. The offset error (OS_e) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 48.)
15. The gain error (G_e) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 48.)
16. The absolute voltage error (A_e) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
17. This should be considered when both analog and digital signals are simultaneously input to port 5.
18. This parameter is guaranteed by design and characterized, but is not production tested.
2000 Nov 10
64