SAA7785 Datasheet, PDF (66/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
Bit
2
Name
FSTCLK
1
TMRRST
0
R
R/W
RW
RW
RO
Function
Fast Clock Enable. When set, the timer counter will use the CCLK clock
instead of the 570 ns clock. This function will reduce the simulation and test
time of the device.
Timer Reset. When set, this bit holds the multimedia timer in reset. The mul-
timedia timer is also reset by the system reset.
Reserved. This bit returns a zero.
MULTIMEDIA TIMER I/O SPACE REGISTERS
TABLE 70 TMSTAT (RW/RO) - MULTIMEDIA TIMER STATUS REGISTER
SONGBASE
D7
D6
D5
D4
D3
D2
R
R
R
R
TPLD
TRE-
Offset 00h
SUME
POR Value
0
0
0
0
0
0
D1
TMINT
D0
TINTEN
0
0
Bit
7:4
3
Name
R
TPLD
2
TRESUME
1
TMINT
0
TINTEN
R/W
RO
RW
RW
WC
RW
Function
Reserved. These bits return zeros.
Timer Preload Indicator. When set, this indicates the timer will start counting
from the values set in the timer count registers. When cleared, the timer will
start counting from zero or its last value when stopped
Timer Resume. When set, the timer will resume counting at the next 570 ns
clock edge. When cleared, the timer will stop counting.
Timer Interrupt. When asserted, the multimedia timer has flagged an inter-
rupt when the timer has counted to zero. The timer will continue to count.
Writing a one to this bit will clear the interrupt.
Timer Interrupt Enable. When set, the multimedia timer will generate an inter-
rupt.
MULTIMEDIA TIMER COUNT REGISTERS
There are three registers required to hold the timer value. These three registers can be read at different cycles, It is rec-
ommended that the least significant byte be read first for the most accuracy.
TABLE 71 TMCOUNT2 (RW/RO) - MULTIMEDIA TIMER COUNT REGISTER 2
SONGBASE
D7
D6
D5
D4
D3
D2
D1
D0
Offset 03h
R
R
R
R
TMCOUNT2[7:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7:4
Name
R
R/W
Function
RO Reserved. These bits return zeros.
1999 Nov 12
66