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SAA7785 Datasheet, PDF (50/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator
Philips Semiconductors
ThunderBird AvengerTM PCI Audio
Accelerator
Preliminary Specification
SAA7785
D7
D6
D5
D4
D3
D2
D1
D0
F_
UDF
MHz66
R
R
R
R
R
BK2BK
POR Value
1
0
0
0
0
0
0
0
Bit
Name
R/W
Function
15
R_PERR
RC Received Parity Error: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger™, function 1 has detected a PCI bus parity error at
least once since this bit was last reset.
14
S_SERR
RC Signalled System Error: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger™, function 1 has reported a system error on the
SERR# signal at least once since this bit was last reset.
13
SM_ABORT RO Signalled Master Abort: The SSA7785 ThunderBird Avenger™, function 1,
does not act as a master.
12
RT_ABORT
RO Received Target Abort: The SSA7785 ThunderBird Avenger™, function 1
does not act as a master.
11
ST_ABORT
RC Signalled Target Abort: When set to 1, this bit indicates that the SSA7785
ThunderBird Avenger™, function 1 has signalled a target abort at least once
since this bit was last reset.
10:9 DEVSEL_TM RO DEVSEL Timing: This field indicates the timing of the DEVSEL output (when
G
a PCI master is accessing a SSA7785 ThunderBird Avenger™, function 1
resource). It always returns 01 (Bin).
00 = Fast
01 = Medium (Default Timing)
10 = Slow
8
S_PERR
RO Signalled Parity Error: The SSA7785 ThunderBird Avenger™, function 1,
does not act as a bus master.
7
F_BK2BK
RO Always returns 1 to indicate support of fast back to back cycles when the
SSA7785 ThunderBird Avenger™, function 1 is the target.
6
UDF
RO User Definable Features. Always returns 0.
5
MHz66
RO 66 MHz Capable. Always returns 0.
4:0 R
RO Reserved. These bits always return zero.
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged.
TABLE 38 Revision ID Register - REVISION (RO)
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 08h
REVISION_ID[7:0]
POR Value
0
0
0
0
0
0
0
0
1999 Nov 12
50