SAA7785 Datasheet, PDF (20/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
STOP#
TRDY#
PAR
PCREQ#
PCGNT#
REQ#
PCI Bus Stop (Target Initiated Termination)
When the SAA7785 is a PCI master, STOP# is an input which causes the SAA7785 to com-
plete, abort or retry the transfer, depending on the state of TRDY# and DEVSEL#.
When the SAA7785 is a PCI slave, it drives STOP# as active (LOW) to terminate or retry a
transaction.
PCI Bus Target Ready
When the SAA7785 is a PCI master, TRDY# is an input which indicates the target agent’s abil-
ity to complete the data phase of the transaction. After initiation of a PCI bus transaction, the
SAA7785 inserts wait cycles until TRDY# is sampled active.
When the SAA7785 is a PCI slave, it drives TRDY# active to indicate that the SAA7785 has
sampled the data from AD[31:0] during a write phase, or presented valid data on AD[31:0] dur-
ing a read phase.
PCI Bus Parity
When the SAA7785 is a PCI master, it drives PAR to reflect the correct value for even parity on
the AD[31:0] and C/BE#[3:0] buses one clock after the address phase and after each write data
phases.
When the SAA7785 is a PCI slave, it drives PAR to reflect the correct value for even parity on
the AD[31:0] and C/BE#[3:0] buses one clock after completion of each read data phase.
PC/PCI DMA Request
This signal requests DMA series from an external chipset that supports PC/PCI protocols. The
SAA7785 chip asserts PCGNT# according to the desired DMA channel required by either the
SoundBlaster or AC97 interfaces. The requested channel is encoded serially on the PCGNT#
pin.
The SAA7785 will become the bus owner when it receives an asserted PCGNT# signal. This
handshaking is synchronous to PCLK.
PC/PCI DMA Grant
An asserted PCGNT# pin indicates that the external PC/PCI master arbiter has granted DMA
services to the encoded DMA channel to the requesting DMA agent on the SAA7785 chip.
PCI Bus Request
This signal controls the PCI bus arbitration between the SAA7785 chip and the PCI master
arbiter. When REQ# is asserted, the SAA7785 indicates a desire to become the PCI bus owner.
The SAA7785 will become the bus owner when it receives an asserted grant signals (GNT# is
LOW). This handshaking is synchronous to PCLK.
REQ# is three-stated while RST# is active.
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