SAA7785 Datasheet, PDF (42/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
Bit
31:2
1
0
Name
MDBASE
R
IO
R/W
RW
RO
RO
Function
MIDI port programmable base address. The address should be on a double word
boundary. For reference the MIDI port legacy base addresses are 220h, 230h,
240h, 250h, 300h, 320h, 330h, 332h, 334h, 336h, 340h, and 360h.
Reserved. This bit is reserved a must always return a zero for plug and play.
I/O flag. This read only bit indicates that this is an I/O range.
TABLE 23 ADLIB Base Address Register - ALBASE (RW/RO)
PCI CFG 0
D31
D30
D29
D28
D27
D26
D25
D24
Offset 1Ch
ALBASE[31:24]
POR Value
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
ALBASE[23:16]
POR Value
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
ALBASE[15:8]
POR Value
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
ALBASE[7:3]
R
R
IO
POR Value
0
0
0
0
0
0
0
1
Bit
31:3
Name
ALBASE
2:1 R
0
IO
R/W
RW
RO
RO
Function
AdLib registers programmable base address. The address should be on a quad
word (64 bit) boundary. For reference, the AdLib legacy base address is at 388h
and maps into a subset of the Sound Blaster registers.
Reserved. These bits are reserved and always return zeros for plug and play.
I/O flag. This read only bit indicates that this is an I/O range.
TABLE 24 Subsystem Vendor ID - SUBVENID (RO)
PCI CFG 0
D15
D14
D13
D12
D11
D10
D9
D8
Offset 2Ch
SUBVEN_ID[15:8]
1999 Nov 12
42