SAA7785 Datasheet, PDF (49/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
POR Value
D7
STEP-
PING
0
D6
PERR_
RESP
0
D5
SNOOP_
ENB
0
D4
MEM_
INV_EN
0
D3
SPEC_
CNTL
0
D2
MAST_
CNTL
0
D1
MEM_
CNTL
0
D0
IO_
CNTL
0
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Name
R
FBACK_ENB
SERR_RESP
STEPPING
PERR_RESP
SNOOP_ENB
MEM_INV_EN
SPEC_CNTL
MAST_CNTL
MEM_CNTL
IO_CNTL
R/W
RO
RO
RW
RO
RW
RO
RO
RO
RO
RO
RW
Function
Reserved. These bits always return zero.
Fast Back-to-Back Enable: the SSA7785 ThunderBird Avenger™, function 1
does not support fast back to back master cycles therefore this bit always
returns a zero.
System Error Response: When set to 1, the SSA7785 ThunderBird
Avenger™, function 1 responds to detected PCI bus address parity errors by
asserting SERR#. When 0, the SSA7785 ThunderBird Avenger™ ignores
these errors.
Address / Data Stepping: Always returns 0.
Parity Error Response: When set to 1, the SSA7785 ThunderBird Avenger™,
function 1 responds to detected PCI bus data parity errors by asserting
PERR#. When 0, the SSA7785 ThunderBird Avenger™ ignores PCI bus data
parity errors.
VGA Snoop Enable. The SSA7785 ThunderBird Avenger™, function 1 does
not support VGA snoop enable, therefor this bit always returns a zero.
Memory Write and Invalidate Enable: Always returns 0.
Special Cycle Control: Controls the devices ability to respond to Special
Cycle Operations. A value of 0 causes the SSA7785 ThunderBird Avenger™,
function 1 to ignore all Special Cycles.
Master Control: The SSA7785 ThunderBird Avenger™, function 1 does not
have any master functions.
Memory Response Control: The SSA7785 ThunderBird Avenger™, function 1
does not support target memory cycles therefore this bit always returns a
zero.
I/O Response Control: Controls the SSA7785 ThunderBird Avenger™, func-
tion 1’s response to I/O space. A value of 0 disables the device response. A
value of 1 allows the device to respond to I/O space accesses.
TABLE 37 Status Register - STATUS (RO/RW)
PCI CFG 1
Offset 06h
POR Value
D15
D14
R_PERR S_SERR
0
0
D13
SM_
ABORT
0
D12
RT_
ABORT
0
D11
ST_
ABORT
0
D10
D9
DEVSEL_TMG
0
1
D8
S_PERR
0
1999 Nov 12
49