SAA7785 Datasheet, PDF (52/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
POR Value
0
0
0
0
0
0
0
0
Bit
7:0
Name
LATIME
R/W
RO
Function
The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. It is set to zero since the joystick is a target
only.
TABLE 42 Header Type Register - HEADER (RO)
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value
1
0
0
0
0
0
0
0
Bit
7
Name
MULTI_FN
6:0 HEADER
R/W
RO
RO
Function
For the SSA7785 ThunderBird Avenger™, function 1, this bit has no mean-
ing.
Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
TABLE 43 BIST Register - BIST (RO)
PCI CFG 1
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Fh
BIST
START
R
R
CODE[3:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7
Name
BIST
6
START
5:4 R
3:0 CODE
R/W
RO
RO
RO
RO
Function
BIST capable. BIST is not supported in the SSA7785 ThunderBird
Avenger™, function 1 at this revision.
If BIST capable, this bit will start the BIST. Writing a 1 will start the test and
the BIST should write this bit to a zero when complete. Software should fail
the device if the BIST is not complete after 2 seconds.
Reserved. These bits always return zero.
Completion Code. A value of zero means the device has passed its test.
Non-zero values means the device has failed using device specific failure
codes.
SSA7785 ThunderBird Avenger™ CFG Space 1 Legacy Base Address Registers
1999 Nov 12
52