SAA7785 Datasheet, PDF (61/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
Bit
7
Name
MULTI_FN
6:0 HEADER
R/W
RO
RO
Function
For the SSA7785 ThunderBird Avenger™, function 2, this bit has no mean-
ing.
Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
TABLE 61 BIST Register - BIST (RO)
PCI CFG 2
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Fh
BIST
START
R
R
CODE[3:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7
Name
BIST
6
START
5:4 R
3:0 CODE
R/W
RO
RO
RO
RO
Function
BIST capable. BIST is not supported in the SSA7785 ThunderBird
Avenger™, function 2 at this revision.
If BIST capable, this bit will start the BIST. Writing a 1 will start the test and
the BIST should write this bit to a zero when complete. Software should fail
the device if the BIST is not complete after 2 seconds.
Reserved. These bits always return zero.
Completion Code. A value of zero means the device has passed its test.
Non-zero values means the device has failed using device specific failure
codes.
SSA7785 ThunderBird Avenger™ CFG Space 1 Legacy Base Address Registers
The SSA7785 ThunderBird Avenger™, contains one legacy I/O base registers in configuration space 1. The joystick is
the sole legacy I/O base address register and is documented here.
TABLE 62 16650 UART Base Address - UARTBASE (RW/RO)
PCI CFG 2
D31
D30
D29
D28
D27
D26
D25
D24
Offset 10h
UARTBASE[31:24]
POR Value
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
UARTBASE[23:16]
POR Value
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
1999 Nov 12
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