SAA7785 Datasheet, PDF (38/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
TABLE 17 Master Latency Timer Register - LATIME (RW)
PCI CFG 0
D7
D6
D5
D4
D3
Offset 0Dh
LATIME[7:0]
POR Value
0
0
0
0
0
Preliminary Specification
SAA7785
D2
D1
D0
0
0
0
Bit
7:0
Name
LATIME
R/W
RW
Function
The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. The timer is reloaded at each assertion of
FRAME# by the primary master. If the primary master loses its bus grant,
then it must relinquish the bus after the timer expires.
TABLE 18 Header Type Register - HEADER (RO)
PCI CFG 0
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value
1
0
0
0
0
0
0
0
Bit
7
Name
MULTI_FN
R/W
RO
Function
A 1 indicates that the SSA7785 ThunderBird Avenger™ is a multi-function
device. The three PCI configuration headers are accessed by the configura-
tion cycle address bits 10-8. The function definitions are as follows:
0 = Audio Subsystem
1 = Joystick
2 = 16650 UART
6:0 HEADER
RO Header Type. A 00h indicates this device is a not a PCI-to-PCI bridge.
TABLE 19 BIST Register - BIST (RO)
PCI CFG 0
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Fh
BIST
START
R
R
CODE[3:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7
Name
BIST
R/W
RO
Function
BIST capable. BIST is not supported in the SSA7785 ThunderBird
Avenger™, function 0 at this revision. It may be desired to include a BIST test
for the DSP at a later time.
1999 Nov 12
38