SAA7785 Datasheet, PDF (47/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
Preliminary Specification
ThunderBird Avenger^TM PCI Audio
Accelerator
SAA7785
TABLE 32 Miscellaneous Configuration Register - MSCCFG (RO/RW)
PCI CFG 0
Offset 58h
POR Value
D7
D6
ASYMCLK[1:0]
0
0
D5
D4
RDY_EN CFGCLK
D3
BHEN
0
0
0
D2
D1
PCCH[1:0]
0
0
D0
PCPCI
_EN
0
Bit
7:6
Name
ASYMCLK
5
RDY_EN
4
CFGCLK
3
BHEN
2:1 PCCH
0
PCPCI_EN
R/W
RW
RW
RW
RW
RW
RW
Function
Asymmetrical Clock Select. These bits program the duty cycle for the input
for the two phase DSP clock generator.
Music registers ready enable. When set, the music registers will cause the
PCI interface to retry when either of the music registers (music0 or music1)
are full.
Serial Configuration Port Clock Select. This bit selects the clock output to the
Configuration Serial Port.
0 = Ouput a 400 KHz clock. Incoming data will be synchronized to this clock.
1 = Output the PCI clock.
Bus Hog Fix Enable.
These two bits are the encoded channel number that the soundblaster will be
on in the PC/PCI mode and are valid only when the PC/PCI mode is enabled.
PC/PCI mode enable bit. This bit, when set = 1, will enable the PC/PCI side-
band signals for the Soundblaster legacy mode.
PCI Configuration Space 1
The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with
the PCI interface (offset 00h - 3Ch) will be detailed following SSA7785 ThunderBird Avenger™. The remainder of the
registers will be detailed with the blocks they control. This register space is for the joystick.
TABLE 33 PCI Configuration Space 1 Register Map
Byte 3
BIST
Max_Lat
Byte 2
Device ID
Status
Class Code
Header Type
Subsystem ID
Min_Gnt
Byte 1
Byte 0
Vendor ID
Command
Revision ID
Master Latency Timer
Cache Line Size
GMBASE
Reserved
Subsystem Vendor ID
Reserved
Interrupt Pin
Interrupt Line
Reserved
Offset
00h
04h
08h
0Ch
10h
14-2B
2Ch
30-3Bh
3Ch
40-6Bh
1999 Nov 12
47