SAA7785 Datasheet, PDF (65/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
FIGURE 7
MULTIMEDIA TIMER BLOCK DIAGRAM
CCLK
CLOCK
DIVIDE
LOGIC
COUNTER CLOCK
Preliminary Specification
SAA7785
PS BUS
CTL
INTERNAL
PS BUS
INTERFACE
CTL
COUNT
INTR
20 BIT - 1uS
RESOLUTION
UP COUNTER
INTERRUPT
GENERATION
LOGIC
MULTIMEDIA TIMER REGISTER DEFINITION
There are five registers that control the multimedia timer. These registers are the timer control register, timer status, and
timer count registers. The timer control register resides in PCI configuration space. The remainder of the timer registers
are in I/O space.
MULTIMEDIA TIMER PCI CONFIGURATION REGISTERS
TABLE 69 TIMRCFG0 (RW/RO) - MULTIMEDIA TIMER CONFIG REGISTER 0
PCI CFG 0
D7
D6
D5
D4
D3
D2
D1
D0
Offset 64h
R
R
R
R
R
FSTCLK TMRRST
R
POR Value
0
0
0
0
0
0
0
0
Bit
7:3
Name
R
R/W
Function
RO Reserved. These bits return zeros.
1999 Nov 12
65