SAA7785 Datasheet, PDF (28/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
Preliminary Specification
ThunderBird Avenger^TM PCI Audio
Accelerator
SAA7785
The PCI datapath block contains the multiplexors and registers to steer the data to and from the PCI interfaces. The
data is de-multiplexed from the external PCI interface to the internal master and slave busses. Control logic from the
master and slave devices control the datapath.
The SSA7785 ThunderBird Avenger™ is considered a multi-function device since the operating system may wish to
load different drivers for certain functions. These functions are the audio subsystem, the joystick and the 16650 UART.
Each of these major functions must have a separate PCI configuration space. The standard PCI configuration header
for these three functions are supported in the PCI interface.
The SSA7785 ThunderBird Avenger™ PCI interface responds to and initiates PCI cycles with positive decoding
according to the PCI 2.1 specification. The interface asserts DEVSEL# after the first clock following FRAME# making it
a medium responder. For specific LAM cycles, the SSA7785 ThunderBird Avenger™ will be a fast responder. SSA7785
ThunderBird Avenger™ indicates which cycles the PCI interface responds to or initiates.
TABLE 5 PCI Bus Command Definitions and SSA7785 ThunderBird Avenger™ Responses
c/be#[3:0]
Command Type
SSA7785 ThunderBird Avenger™ Response to Cycle
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
This cycle is not claimed.
This cycle is not claimed.
All I/O Read cycles directed to the SSA7785 ThunderBird
Avenger™ are claimed by the target interface.
All I/O Write cycles directed to the SSA7785 ThunderBird
Avenger™ are claimed by the target interface.
This cycle is not claimed.
This cycle is not claimed.
This cycle is not claimed.
This cycle is not claimed.
This cycle is not claimed.
This cycle is not claimed.
All Configuration Read cycles are claimed by the target interface
provided IDSEL is sampled asserted during the address/cmd
phase.
All Configuration Write cycles are claimed by the target interface
provided IDSEL is sampled asserted during the address/cmd
phase.
This cycle is not claimed.
The SSA7785 ThunderBird Avenger™ supports 32-bit
addresses only.
This cycle is not claimed.
This cycle is not claimed.
The SSA7785 ThunderBird Avenger™ will respond to byte, word, tri-byte or double word access for configuration read
and configuration write cycles provided PCI addressing rules are followed. Byte and word width accesses allowed for
I/O cycles depend largely on the target I/O device. In general, 24-bit and 32-bit accesses are not allowed to I/O devices
and will result in a target abort. The SSA7785 ThunderBird Avenger™ performs double word accesses when initiating
1999 Nov 12
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