SAA7785 Datasheet, PDF (60/68 Pages) NXP Semiconductors – ThunderBird Avenger PCI Audio Accelerator

Philips Semiconductors
ThunderBird Avenger^TM PCI Audio
Accelerator
Preliminary Specification
SAA7785
PCI CFG 2
D23
D22
D21
D20
D19
D18
D17
D16
D7
D6
D5
D4
D3
D2
D1
D0
PGM_IFACE[7:0]
POR Value
0
0
0
0
0
0
1
0
Bit
23:16
15:8
7:0
Name
BASE_CLASS
SUB_CLASS
PGM_IFACE
R/W
RO
RO
RO
Function
The base class of 07h describes simple communication devices.
The sub class of 00h describes serial controllers.
The interface of 02h details a 16550 compatible serial controller.
TABLE 58 CACHELINE Size Register - CACHELINE (RO)
PCI CFG 2
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Ch
CACHELINE[7:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7:0
Name
CACHELINE
R/W
Function
RO Reserved for cache line size indicator.
TABLE 59 Master Latency Timer Register - LATIME (RW)
PCI CFG 2
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Dh
LATIME[7:0]
POR Value
0
0
0
0
0
0
0
0
Bit
7:0
Name
LATIME
R/W
RO
Function
The primary bus latency timer specifies the number of primary clocks that the
primary master may consume. It is set to zero since the 16650 UART is a tar-
get only.
TABLE 60 Header Type Register - HEADER (RO)
PCI CFG 2
D7
D6
D5
D4
D3
D2
D1
D0
Offset 0Eh
MULTI_
FN
HEADER[6:0]
POR Value
1
0
0
0
0
0
0
0
1999 Nov 12
60