XA-S3 Datasheet, PDF (48/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
EPROM CHARACTERISTICS
The XA-S3 is programmed by using a modified Improved
Quick-Pulse Programming™ algorithm. This algorithm is essentially
the same as that used by 80C51 family EPROM parts. However
different pins are used for many programming functions.
The XA-S3 contains three signature bytes that can be read and
used by an EPROM programming system to identify the device. The
signature bytes identify the device as an XA-S3 manufactured by
Philips.
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. When only security bit 1 is programmed,
MOVC instructions executed from external program memory are
disabled from fetching code bytes from the internal memory. All
further programming of the EPROM is disabled. When security bits
1 and 2 are programmed, in addition to the above, verify mode is
disabled. When all three security bits are programmed, all of the
conditions above apply and all external program memory execution
is disabled. (See Table 6.)
Table 6. Program Security Bits
PROGRAM LOCK BITS
SB1 SB2 SB3 PROTECTION DESCRIPTION
1
U
U
U No Program Security features enabled.
2
P
U
U MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory and further programming of the EPROM is disabled.
3
P
P
U Same as 2, also verify is disabled.
4
P
P
P Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
ROM CODE SUBMISSION
When submitting ROM code for the XA-S3, the following must be specified:
1. 32k byte user ROM data
2. ROM security bits.
ADDRESS
0000H to 7FFFH
8020H
8020H
CONTENT
DATA
SEC
SEC
BIT(S)
7:0
0
1
8020H
SEC
3
COMMENT
User ROM Data
ROM Security Bit 1
ROM Security Bit 2
0 = enable security
1 = disable security
ROM Security Bit 3
0 = enable security
1 = disable security
™Trademark phrase of Intel Corporation.
2000 Dec 01
48