XA-S3 Datasheet, PDF(12/52 Page) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

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XA-S3 Datasheet, PDF (12/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

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Philips Semiconductors

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 Vâ5.5 V),

I2C, 2 UARTs, 16 MB address range

Preliminary specification

XA-S3

NAME

S1ADEN

SCR

DESCRIPTION

Serial port 1 address enable

System configuration register

SSEL*

Segment selection register

SFR

Address

466

440

403

MSB

21F

ESWEN

BIT FUNCTIONS AND ADDRESSES

Reset

LSB Value

00h

PT1

PT0

PZ 00h

21E

21D

21C 21B

21A

219

218

R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG 00h

SWE

Software interrupt enable

47A

SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00h

357

356

355

354

353

352

351

350

SWR*

Software interrupt request

42A

SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00h

2C7

2C6

2C5

2C4 2C3

2C2

2C1 2C0

T2CON* Timer 2 control register

418

TF2 EXF2 RCLK0 TCLK0 EXEN2 TR2 C/T2 CP/RL2 00h

2CF

2CE 2CD 2CC 2CB 2CA 2C9 2C8

T2MOD* Timer 2 mode control

419

â RCLK1 TCLK1 â

T2OE DCEN 00h

TH2

Timer 2 high byte

459

00h

TL2

Timer 2 low byte

458

00h

T2CAPH Timer 2 capture, high byte

45B

00h

T2CAPL Timer 2 capture, low byte

45A

00h

287

286

285

284

283

282

281

280

TCON* Timer 0 and 1 control register

410

TF1

TR1

TF0 TR0

IE1

IT1

IE0

IT0 00h

TH0

Timer 0 high byte

451

00h

TH1

Timer 1 high byte

453

00h

TL0

Timer 0 low byte

450

00h

TL1

Timer 1 low byte

452

00h

TMOD

Timer 0 and 1 mode control

45C GATE C/T

M0 GATE C/T

M0 00h

28F

28E

28D 28C 28B 28A 289

288

TSTAT* Timer 0 and 1 extended status 411

T1OE

T0OE 00h

2FF

2FE

2FD 2FC 2FB 2FA

2F9

2F8

WDCON* Watchdog control register

41F PEW2 PRE1 PRE0

WDRUN WDTOF

Note 6

WDL

Watchdog timer reload

45F

00h

WFEED1 Watchdog feed 1

45D

WFEED2 Watchdog feed 2

45E

NOTES:

* SFRs are bit addressable.

# SFRs are modified from or added to XA-G3 SFRs.

1. At reset, the BCR is loaded with the binary value 00000a11, where âaâ is the value on the BUSW pin. This defaults the address bus size to 24 bits.

2. SFR is loaded from the reset vector.

3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.

4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other

purposes in future XA derivatives. The reset value shown for these bits is 0.

5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the

condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins

execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that

are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference.

6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.

7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0.

8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an

interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an

instruction that performs a read-modify-write operation. Examples of such instructions are:

and

s0con,#$fb

clr

tr0

setb

ti_0

XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in

I2CON); TI_0 and RI_0 (in S0CON); TI_1 and RI_1 (in S1CON); FE0, BR0, and OE0 (in S0STAT); FE1, BR1, and OE1 (in S1STAT); TF2 (in

T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON).

9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts

to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.

2000 Dec 01

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