XA-S3 Datasheet, PDF (36/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
10-BIT¹⁰ MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
T_amb = 0 to +70°C for commercial, T_amb = –40 to +85°C for industrial, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
LIMITS
MAX
UNIT
AV_DD
Analog supply voltage
2.7
AI_DD
Analog supply current (operating)
Port 5 = 0 to AV_DD
AI_ID
Analog supply current (Idle mode)
AI_PD
Analog supply current (Power-Down mode) Commercial temperature range
Industrial temperature range
3.3
V
2.5
mA
2.5
µA
100
µA
150
µA
AV_IN
Analog input voltage
AV_SS –0.2
AV_DD +0.2
V
R_REF
Resistance between V_REF+ and V_REF–
125
225
kΩ
C_IA
Analog input capacitance
15
pF
DL_e
Differential non-linearity^{1, 2, 3}
±1 ⁹
LSB
IL_e
Integral non-linearity^{1, 4}
±2.5 ⁹
LSB
OS_e
G_e
Offset error^{1, 5}
Gain error^{1, 6}
±6 ⁹
LSB
±1 ⁹
%
A_e
Absolute voltage error (with averaging)^{1, 7}
±8 ⁹
LSB
M_CTC
Channel-to-channel matching
±1
LSB
C_t
Crosstalk between inputs of port⁸
0 – 100 kHz
–60
dB
NOTES:
1. Conditions: AV_REF– = 0 V; AV_REF+ = 3.07 V.
2. The differential non-linearity (DL_e) is the difference between the actual step width and the ideal step width. See Figure 25.
3. The ADC is monotonic, there are no missing codes.
4. The integral non-linearity (IL_e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 25.
5. The offset error (OS_e) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
the straight line which fits the ideal transfer curve. See Figure 25.
6. The gain error (G_e) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25.
7. The absolute voltage error (A_e) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design.
9. 10-bit mode only.
10. 10-bit mode is only operational up to f_C = 20 MHz.
2000 Dec 01
36