XA-S3 Datasheet, PDF (19/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when the I²C
interface is in a master mode. An I²C rate of 100kHz or lower is
typical and can be derived from many oscillator frequencies. The
various serial rates are shown in Table 4. A variable bit rate may
also be used if Timer 1 is not required for any other purpose while
the I²C hardware is in a master mode. The frequencies shown in
Table 4 are unimportant when the I²C hardware is in a slave mode.
In the slave modes, the hardware will automatically synchronize with
the incoming clock frequency.
The I²C Status Register, I2STA
I2STA is an 8-bit read-only special function register. The three least
significant bits are always zero. The five most significant bits contain
the status code. There are 26 possible status codes. When I2STA
contains F8H, no relevant state information is available and no serial
interrupt is requested. All other I2STA values correspond to defined
hardware interface states. When each of these states is entered, a
serial interrupt is requested (SI = “1”).
NOTE: A detailed I²C interface description and usage
information, including example driver code, will be provided in
a separate document.
Table 4. I²C Rate Control
Frequency Select
(CR2, CR1, CR0)
Clock Divisor
8 MHz
Example I²C Rates at Specific Oscillator Frequencies
12 MHz
16 MHz
20 MHz
24 MHz
30 MHz
0h (0000)
1h (0001)
20
(400)¹
–
–
–
–
–
40
(200)¹
(300)¹
(400)¹
–
–
–
2h (0010)
3h (0011)
68
(116.65)¹
(176.46)¹
(235.29)¹
(294.12)¹
(352.94)¹
–
88
90.91
(136.36)¹
(181.82)¹
(227.27)¹
(272.73)¹
(340.91)¹
4h (0100)
5h (0101)
160
50
75
100
(125)¹
(150)¹
(187.5)¹
272
29.41
44.12
58.82
73.53
88.24
(110.29)¹
6h (0110)
352
22.73
34.09
45.45
56.82
68.18
85.23
7h (0111)
(Timer 1)²
(Timer 1)²
(Timer 1)²
(Timer 1)²
(Timer 1)²
(Timer 1)²
(Timer 1)²
NOTES:
1. The XA-S3 I²C interface does not conform to the 400kHz I²C specification (which applies to rates greater than 100kHz) in all details, but
may be used with care where higher rates are required by the application.
2. The timer 1 overflow is used to clock the I²C interface. The resulting bit rate is 1/2 of the timer overflow rate.
2000 Dec 01
19