XA-S3 Datasheet, PDF (17/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
A/D Accuracy
The XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
1.50
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by ±1.25 LSB.
1.25
1.00
0.75
0.50
0.25
0.00
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Number of Samples
Figure 5. A/D accuracy by number of averaging samples
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to f_C = 20 MHz.)
15 16
SU01227
I2CON Address:42Ch
Bit Addressable
Reset Value: 00h
BIT
I2CON.7
I2CON.6
I2CON.5
SYMBOL
CR2
ENA
STA
I2CON.4
I2CON.3
STO
SI
I2CON.2 AA
I2CON.1
I2CON.0
CR1
CR0
MSB
CR2 ENA STA STO
SI
LSB
AA
CR1 CR0
FUNCTION
I²C Rate Control, with CR1 and CR0. See text and table.
Enable I²C port. When ENA = 1, the I²C port is enabled.
Start flag. Setting STA to 1 causes the I²C interface to attempt to gain mastership of the bus by
generating a Start condition.
Stop flag. Setting STO to 1 causes the I²C interface to attempt to generate a Stop condition.
Serial Interrupt. SI is set by the I²C hardware when a new I²C state is entered, indicating that
software needs to respond. SI causes an I²C interrupt if enabled and of sufficient priority.
Assert Acknowledge. Setting AA to 1 causes the I²C hardware to automatically generate
acknowledge pulses for various conditions (see text).
I²C Rate Control, with CR2 and CR0. See text and table.
I²C Rate Control, with CR2 and CR1. See text and table.
SU00941
Figure 6. I²C Control Register (I2CON)
2000 Dec 01
17