XA-S3 Datasheet, PDF (40/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
AC ELECTRICAL CHARACTERISTICS (3 V)
V_DD = 2.7 V to 4.5 V; T_amb = 0 to +70°C for commercial, T_amb = –40°C to +85°C for industrial.
SYMBOL FIGURE
PARAMETER
LIMITS
MIN
MAX
Address Cycle
t_LHLL
26, 28, 30
t_AVLL
26, 28, 30
t_LLAX
26, 28, 30
Code Read Cycle
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
(V1 * t_C) – 10
(V1 * t_C) – 18
(t_C/2) – 12
t_PLPH
26
t_LLPL
26
t_AVIVA
26
t_AVIVB
27
t_PLIV
26
t_PHIX
26
t_PHIZ
26
t_IXUA
26
Data Read Cycle
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non-ALE cycle (access time)
PSEN asserted to instruction valid (enable time)
Instruction hold after PSEN de-asserted
Bus 3-State after PSEN de-asserted
Hold time of unlatched part of address after instruction latched
(V2 * t_C) – 12
(t_C/2) – 9
0
0
(V3 * t_C) – 58
(V4 * t_C) – 52
(V2 * t_C) – 52
t_C – 8
t_RLRH
28
t_LLRL
28
t_AVDVA
28
t_AVDVB
29
t_RLDV
28
t_RHDX
28
t_RHDZ
28
t_DXUA
28
Data Write Cycle
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non-ALE cycle (access time)
RD low to valid data in (enable time)
Data hold time after RD de–asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after data latched
(V7 * t_C) – 12
(t_C/2) – 9
0
0
(V6 * t_C) – 58
(V5 * t_C) – 52
(V7 * t_C) – 52
t_C – 8
t_WLWH
30
t_LLWL
30
t_QVWX
30
t_WHQX
30
t_AVWL
30
t_UAWH
30
Wait Input
WR pulse width
ALE falling edge to WR asserted
Data valid before WR asserted (data set-up time)
Data hold time after WR de-asserted (Note 6)
Address valid to WR asserted (address set-up time) (Note 5)
Hold time of unlatched part of address after WR is de-asserted
(V8 * t_C) – 12
(V12 * t_C) – 10
(V13 * t_C) – 28
(V11 * t_C) – 8
(V9 * t_C) – 28
(V11 * t_C) – 10
t_WTH
31
t_WTL
31
NOTES ON PAGE 41.
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
WAIT hold after bus strobe (RD, WR, or PSEN) asserted
(V10 * t_C) – 5
(V10 * t_C) – 40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2000 Dec 01
40