XA-S3 Datasheet, PDF (39/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL FIGURE
PARAMETER
Address Cycle
t_CHLH
26
t_CLLL
26
t_CHAV
26
t_CHAX
26
Code Read Cycle
t_CHPL
26
t_CHPH
26
t_IVCH
26
t_CHIX
26
t_CHIZ
26
Data Read Cycle
t_CHRL
28
t_CHRH
28
t_DVCH
28
t_CHDX
28
t_CHDZ
28
Data Write Cycle
t_CHWL
30
t_CHWH
30
t_QVCH
30
t_CHQX
30
Wait Input
t_CHWTH
31
NOTES ON PAGE 41.
CLKOUT rising edge to ALE rising edge
CLKOUT falling edge to ALE falling edge
CLKOUT rising edge to address valid
CLKOUT rising edge to address changing (hold time)
CLKOUT rising edge to PSEN asserted
CLKOUT rising edge to PSEN de-asserted
Instruction valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to instruction changing (hold time)
CLKOUT rising edge to Bus 3-State (code read)
CLKOUT rising edge to RD asserted
CLKOUT rising edge to RD de-asserted
Data valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to Data changing (hold time)
CLKOUT rising edge to Bus 3-State (data read)
CLKOUT falling edge to WR asserted
CLKOUT rising edge to WR de-asserted
Data valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to Data changing (hold time)
WAIT valid prior to CLKOUT rising edge⁸
LIMITS
MIN
MAX
–
13
–
9
–
18
2
–
–
14
–
12
20
–
0
–
–
t_C–8
–
12
–
10
20
–
0
–
–
t_C–8
–
12
–
10
4
–
0
–
21
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2000 Dec 01
39