XA-S3 Datasheet, PDF(31/52 Page) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

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XA-S3 Datasheet, PDF (31/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

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Philips Semiconductors

XA 16-bit microcontroller

32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 Vâ5.5 V),

I2C, 2 UARTs, 16 MB address range

Preliminary specification

XA-S3

START

BIT

DATA BYTE

ONLY IN STOP

MODE 2, 3 BIT

if 0, sets FE

FEn

BRn

OEn STINTn SnSTAT

SU00598

Figure 22. UART Framing Error Detection

SM0_n SM1_n

SM2_n REN_n

TB8_n

RB8_n TI_n

RI_n SnCON

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND âRECEIVED ADDRESSâ = âPROGRAMMED ADDRESSâ

â WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

â WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

Figure 23. UART Multiprocessor Communication, Automatic Address Recognition

SU00613

Clocking / Baud Rate Generation

Same as for the XA-G3.

I/O Port Output Configuration

Port output configurations are the same as for the XA-G3: open

drain, quasi-bidirectional, push-pull, and off.

External Bus

The external bus operates in the same manner as the XA-G3, but

all 24 address lines are brought out to the outside world. This

allows for a maximum of 16 Mbytes of code memory and 16

Mbytes of data memory.

Clock Output

The CLKOUT pin allows easier external bus interfacing in some

situations. This output reflects the X1 clock input to the XA, but is

delayed to match the external bus outputs and strobes. The default

is for CLKOUT to be on at reset, but it may be turned off via the

CLKD bit that has been added to the BCR register.

Reset

Active low reset input, the same as the XA-G3.

The associated RSTOUT pin provides an external indication via an

active low open drain output when an internal reset occurs. The

RSTOUT pin will be driven low when the RST pin is driven low,

when a Watchdog reset occurs or the RESET instruction is

executed. This signal may be used to inform other devices in a

system that the XA-S3 has been reset.

The latched values of EA and BUSW are NOT automatically

updated when an internal reset occurs. RSTOUT may be used to

apply an external reset to the XA-S3 in order to update the

previously latched EA and BUSW values. However, since RSTOUT

reflects ALL reset sources, it cannot simply be fed back into the RST

pin without other logic.

The reset source identification register (RSTSRC) indicates the cause

of the most recent XA reset. The cause may have been an externally

applied reset signal, execution of the RESET instruction, or a

Watchdog reset. Figure 24 shows the fields in the RSTSRC register.

Power Reduction Modes

The XA-S3 supports Idle and Power Down modes of power

reduction. The idle mode leaves some peripherals running in order

to allow them to activate the processor when an interrupt is

generated. The power down mode stops the oscillator in order to

absolutely minimize power. The processor can be made to exit

power down mode via a reset or one of the external interrupt inputs

(INT0 or INT1). This will occur if the interrupt is enabled and its

priority is higher than that defined by IM3 through IM0. In power

down mode, the power supply voltage may be reduced to the RAM

keep-alive voltage VRAM. This retains the RAM, register, and SFR

contents at the point where power down mode was entered. VDD

must be raised to within the operating range before power down

mode is exited.

2000 Dec 01

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