XA-S3 Datasheet, PDF (41/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL FIGURE
PARAMETER
LIMITS
MIN
MAX
UNIT
Address Cycle
t_CHLH
26
t_CLLL
26
t_CHAV
26
t_CHAX
26
Code Read Cycle
CLKOUT rising edge to ALE rising edge
CLKOUT falling edge to ALE falling edge
CLKOUT rising edge to address valid
CLKOUT rising edge to address changing (hold time)
–
15
ns
–
11
ns
–
29
ns
2
–
ns
t_CHPL
26
t_CHPH
26
t_IVCH
26
t_CHIX
26
t_CHIZ
26
Data Read Cycle
CLKOUT rising edge to PSEN asserted
CLKOUT rising edge to PSEN de-asserted
Instruction valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to instruction changing (hold time)
CLKOUT rising edge to Bus 3-State (code read)
–
16
ns
–
15
ns
30
–
ns
0
–
ns
–
t_C–8
ns
t_CHRL
28
t_CHRH
28
t_DVCH
28
t_CHDX
28
t_CHDZ
28
Data Write Cycle
CLKOUT rising edge to RD asserted
CLKOUT rising edge to RD de-asserted
Data valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to Data changing (hold time)
CLKOUT rising edge to Bus 3-State (data read)
–
20
ns
–
16
ns
28
–
ns
0
–
ns
–
t_C–8
ns
t_CHWL
30
CLKOUT falling edge to WR asserted
–
19
ns
t_CHWH
30
CLKOUT rising edge to WR de-asserted
–
16
ns
t_QVCH
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
t_CHQX
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
Wait Input
t_CHWTH
31
WAIT valid prior to CLKOUT rising edge⁸
30
4
ns
NOTES:
1. Load capacitance for all outputs = 50 pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to
the XA User Guide for details of the bus timing settings.
V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the
ALEW bit = 0, and 1.5 if the ALEW bit = 1.
V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
ALEW bits in the BTRL register.
– For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
– For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if
CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2.
Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.
V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and
5 if CRA1/0 = 11).
V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and
CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11.
V5) This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and
DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and
DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and
5 if DRA1/0 = 11).
2000 Dec 01
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