XA-S3 Datasheet, PDF (22/52 Pages) NXP Semiconductors – XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range

Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I²C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
CMOD Address = 490H
Reset Value = 00H
CIDL WDTE
–
–
–
CPS1
CPS0 ECF
Bit:
7
6
5
4
3
2
1
0
Symbol
CIDL
WDTE
–
CPS1
CPS0
ECF
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
Not implemented, reserved for future use.*
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
0
1
1
CPS0
X
0
1
PCA Timer Count Source
TClk (Osc/4, Osc/16, or Osc/64)
Timer 0 overflow
ECI (PCA External Clock Input (max rate = Osc/4)
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f_OSC = oscillator frequency
SU01306
Figure 10. CMOD: PCA Counter Mode Register
CCON Address = 41AH
Reset Value = 00H
Bit Addressable
CF
CR
Bit:
7
6
–
CCF4 CCF3 CCF2 CCF1 CCF0
5
4
3
2
1
0
Symbol Function
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
Not implemented, reserved for future use*.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01307
Figure 11. CCON: PCA Counter Control Register
2000 Dec 01
22