XA-H4 Datasheet, PDF (38/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
ClkOut
A
RAS (CS)
CASL
WE
D[7:0]
t_CHAV
t_CHAV
RAS ADDRESS
t_CHSL
t_AVSL
t_CHSL
t_CHAV
CAS ADDRESS EVEN
t_CHAH
t_CHAH
t_CHSL
t_AVSL
t_CHAV
CAS ADDRESS ODD
t_CHAH
t_CHSH
t_CHSH
t_CPWH
t_DVSL
LS Byte
t_DVSL
MS Byte
Figure 20. DRAM 16-Bit Write on 8-Bit Bus (FPM or EDO DRAMs)
SU01287
ClkOut
t_CHSL
RAS
t_CLRL
t_CHSH
CASH, CASL
RAS and CAS terminate together. The active low portion of RAS can be programmed to last from 3 to 6 clock cycles.
The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles. See Chapter 3 of the XA-H4 User Manual.
Figure 21. REFRESH
t_RP
RAS
NOTE:
t_RP minimum is specified for each of the 5 individual RAS pins (CS_RAS[5:1])
It is the minimum high time (thus RAS inactive) between two DRAM bus cycles on the same RAS pin.
Figure 22. RAS Precharge Time
SU01288
SU01289
1999 Sep 24
38