XA-H4 Datasheet, PDF (18/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
MMR Name
B0CFG
B0AM
B0TMG
B1CFG
B1AM
B1TMG
B2CFG
B2AM
B2TMG
B3CFG
B3AM
B3TMG
B4CFG
B4AM
B4TMG
B5CFG
B5AM
B5TMG
MBCL
RFSH
Hi-Pri Soft Ints & Pin Mux Control Reg.
XInt2
Read/Write
or Read Only
Size
Address
Offset
Description
Memory Interface (MIF) Registers
R/W
8
280h MIF Bank 0 Config
R/W
8
281h MIF Bank 0 Base Address
R/W
8
282h MIF Bank 0 Timing Params
R/W
8
284h MIF Bank 1 Config
R/W
8
285h MIF Bank 1 Base Address
R/W
8
286h MIF Bank 1 Timing Params
R/W
8
288h MIF Bank 2 Config
R/W
8
289h MIF Bank 2 Base Address
R/W
8
28Ah MIF Bank 2 Timing Params
R/W
8
28Ch MIF Bank 3 Config
R/W
8
28Dh MIF Bank 3 Base Address
R/W
8
28Eh MIF Bank 3 Timing Params
R/W
8
290h MIF Bank 4 Config
R/W
8
291h MIF Bank 4 Base Address
R/W
8
292h MIF Bank 4 Timing Params
R/W
8
294h MIF Bank 5 Config
R/W
8
295h MIF Bank 5 Base Address
R/W
8
296h MIF Bank 5 Timing Params
R/W
8
2BEh MIF Memory Bank Configuration Lock Register
R/W
8
2BFh MIF Refresh Control
Miscellaneous Registers
R/W
16
2D0h Control bits for Hi-Priority Soft Ints, and Pin Mux
R/W
8
2D2h External Interrupt 2 Control
Reset
Value
0Fh
00h
0000h
00h
FUNCTIONAL DESCRIPTION
The XA-H4 functions are described in the following sections.
Because all blocks are thoroughly documented in either the IC25 XA
Data Handbook, or the XA-H4 User Manual, only brief descriptions
are given in this datasheet in conjunction with references to the
appropriate document.
XA CPU
The CPU is a 30 MHz implementation of the standard XA CPU core.
See the XA Data Handbook (IC25) for details. The CPU core is
identical to the G3 core. See the caveat in the next paragraph about
the Bus Interface Unit.
Bus Interface Unit (BIU)
This is the internal Bus, not the bus at the pins. This internal bus
connects the CPU to the MIF (Memory and DRAM Controller.)
WARNING: Immediately after reset, always write BTRH = 51h,
followed by BTRL = 40h, in that order. Once written, do not change
the values in these registers. Follow these two writes with five
NOPS. Never write to the BCR register. It comes out of reset
initialized to 07h, which is the only value that will work.
XA CPU
BIU
External
Memory
and I/O Bus
Internal CPU Bus
MIF and DRAM
Controller
DMA
Channels
x8
SU01273
Figure 1. XA CPU core BIU (Bus Interface Unit)
Timers 0 and 1
Timers 0 and 1 are the standard XA-G3 Timer 0 and 1. Each has an
associated I/O pin and interrupt. See the XA-G3 data sheet in the IC25
XA Data Handbook for details. Many XA derivatives include a standard
XA Timer 2 and standard UARTs. These blocks have been removed in
order to provide other functions on the XA-H4. There is no Timer 2 and
the UARTs have been replaced with full function USARTs.
1999 Sep 24
18