XA-H4 Datasheet, PDF (15/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
MMR Name
USART3 Write Register 0
USART3 Write Register 1
USART3 Write Register 2
USART3 Write Register 3
USART3 Write Register 4
USART3 Write Register 5
USART3 Write Register 6
USART3 Write Register 7
USART3 Write Register 8
USART3 Write Register 9
USART3 Write Register 10
USART3 Write Register 11
USART3 Write Register 12
USART3 Write Register 13
USART3 Write Register 14
USART3 Write Register 15
USART3 Write Register 16
USART3 Write Register 17
USART3 Read Register 0
USART3 Read Register 1
Reserved
USART3 Read Register 3
USART3 Read Register 6
USART3 Read Register 7
USART3 Read Register 8
Reserved
USART3 Read Register 10
Reserved
DMA Control Register Ch.0 Rx
FIFO Control & Status Reg Ch.0 Rx
Segment Register Ch.0 Rx
Buffer Base Register Ch.0 Rx
Buffer Bound Register Ch.0 Rx
Address Pointer Reg Ch.0 Rx
Byte Count Register Ch.0 Rx
Data FIFO Register Ch.0 Lo Rx
Data FIFO Register Ch.0 Hi Rx
DMA Control Register Ch.1 Rx
FIFO Control & Status Register Ch.1 Rx
Segment Register Ch. 1 Rx
Read/Write
or Read Only
Size
Address
Offset
Description
USART3 Registers
R/W
8
8C0h Command register
R/W
8
8C2h Tx/Rx Interrupt & data transfer mode
R/W
8
8C4h Extended Features Control
R/W
8
8C6h Receive Parameter and Control
R/W
8
8C8h Tx/Rx miscellaneous parameters & mode
R/W
8
8CAh Tx parameter and control
R/W
8
8CCh HDLC/SDLC address field or Match Character 0
R/W
8
8CEh HDLC/SDLC flag or Match Character 1
R/W
8
8D0h Transmit Data Buffer
R/W
8
8D2h Master Interrupt control
R/W
8
8D4h Miscellaneous Tx/Rx control register
R/W
8
8D6h Clock Mode Control
R/W
8
8D8h Lower Byte of Baud rate time constant
R/W
8
8DAh Upper Byte of Baud rate time constant
R/W
8
8DCh Miscellaneous Control bits
R/W
8
8DEh External/Status interrupt control
R/W
8
8E8h Match Character 2 (WR16)
R/W
8
8EAh Match Character 3 (WR17)
RO
8
8E0h Tx/Rx buffer and external status
RO
8
8E2h Receive condition status/residue code
8E4h
RO
8
8E6h Interrupt Pending Bits
RO
8
8ECh SDLC byte count low register
RO
8
8EEh SDLC byte count high and FIFO status
RO
8
8F0h Receive Buffer
8F2h
RO
8
8F4h Loop/clock status
8F6-8FEh
Rx DMA Registers
R/W
8
100h Control Register
R/W
8
101h Control & Status Register
R/W
8
102h Points to 64 k data segment
R/W
8
104h
Wrap Reload Value for A15 – A8, A7 – A0 reloaded
to zero by hardware
R/W
16
106h Upper Bound (plus 1) on A15 – A0
R/W
16
108h Current Address pointer A15 – A0
R/W
16
10Ah
Corresponds to A15 – A0 Byte Count, generates
interrupt if enabled and byte count exceeded.
10Ch = Byte 0 = older,
R/W
16
10Ch
10Dh = Byte 1 = younger
10Eh = Byte 2 = older,
R/W
16
10Eh
10Fh = Byte 3 = younger
R/W
8
110h Control Register
R/W
8
111h Control & Status Register
R/W
8
112h Points to 64 k data segment
Reset
Value
00h
xx
xx
00h
00h
00h
00h
xx
xx
xx
00h
xx
00h
00h
xx
f8h
00h
00h
–
00h
00h
00h
00h
0000h
0000h
0000h
00h
00h
00h
00h
00h
00h
00h
1999 Sep 24
15