XA-H4 Datasheet, PDF (25/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
The XA-H4 has a standard XA CPU Interrupt Controller,
implemented with 15 Maskable Event Interrupts. Event Interrupts
are defined as maskable interrupts usually generated by hardware
events. However, in the XA-H4, 4 of the 15 Event Interrupts are
generated by software writing directly to the interrupt flag bit. These
4 interrupts are referred to as “High Priority Software Interrupts.”
See the IC25 XA Data Handbook for a full explanation of the
exception structure, including event interrupts, of the XA CPU.
Because the High Priority Software Interrupts are not implemented
on all XA derivitives, they are explained in the XA-H4 User Manual.
XA Core
Interrupt Controller
CTS0
CD0
CTS1
CD1_INT2
CTS2
CD2
CTS3
CD3
INT0
INT1
DMA
Interrupts
USART0/
USART1
INT2
USART2/
USART3
DMAH
DMAL
Autobaud
3–0
Timer 0
Timer 1
Interrupt
Enable/
Disable Bits
Master
Enable
“EA”
Interrupt
To XA CPU
High Priority
4
Software Ints
HSWR 3–0
Figure 6. XA-H4 Interrupt Structure Overview
SU01276
1999 Sep 24
25