XA-H4 Datasheet, PDF (23/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
Receive DMA Channel Modes
The Rx DMA channels have four DMA modes specifically designed
for various applications of the attached USARTs. These modes are
summarized in Table 6. For full details on implementation and use,
see the XA-H4 User Manual.
Table 6. Rx DMA modes summary
Mode
SDLC/HDLC
Rx Chaining
Byte Count Source
DMA stores byte count in header in
memory with data packet.
Periodic
Interrupt
Loaded by processor into DMA,
used only to determine the number
of bytes between interrupts.
Processor can infer the byte count
from the DMA address pointer.
Asynchronous Byte Count can be calculated by
Character
software from the DMA address
Time Out
pointer.
Asynchronous Byte Count can be calculated by
Character
software from the DMA address
Match
pointer.
Maskable Interrupt
Description
At end of received packet
When a complete or aborted SDLC/HDLC packet has
been received, the packet byte count and status
information are stored in memory with the packet. A
maskable interrupt is generated.
When Byte Counter reaches
zero and is reloaded by
DMA hardware from the byte
count register.
The DMA channel runs until commanded to stop by the
processor. It generates a maskable interrupt once per n
bytes, where n is the number written once into the byte
count register by the processor, thus an interrupt is
generated once every n received bytes.
If no character is received
within a specified time out
period, then interrupt.
Processor specifies time out period between incoming
characters. If no character is received within that time,
a maskable interrupt is generated.
When matched character is
stored in memory.
There are four match registers, each incoming character
is received within that time, a maskable interrupt is
generated. When a matched character is stored in
memory by DMA, a maskable interrupt is generated.
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Rx Time Out
Rx Channel
Data FIFO 3
Data FIFO 1
Data FIFO 2
Data FIFO 0
DMA Control
Segment
Buffer Base
Buffer Bound
Address Pointer
Byte Count
FIFO Control
Figure 5. Rx and Tx DMA Registers
Tx Channel
SU01240
1999 Sep 24
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