XA-H4 Datasheet, PDF (2/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
DESCRIPTION
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced USARTs help solve I/O
intensive tasks with a minimum of CPU load.
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
FEATURES
• Large Memory Support
• De-multiplexed Address/Data Bus
• Six Programmable Chip Selects
– Support for Unified Memory – allows easy user modification of
all code
– External ISP Flash support for easy code download
• Dynamic Bus Sizing – each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
• Dynamic Bus Timing – each of 6 chip selects has individual
programmable bus timing.
• 32 Programmable General Purpose I/O Pins
• Four USARTs with 230.4 kbps capability
• Eight DMA Channels
ADDITIONAL XA-H4 FEATURES (NOT AVAILABLE ON XA-H3)
• Complete DRAM controller supports up to four banks of 8 MB each
• Memory controller supports 16 MB in Unified Mode
– Four Match Characters are supported on each USART in
Async Mode
– Hardware Autobaud on all four USARTs in Async Mode
• Memory controller supports 32 MB in Harvard Mode
– USARTs are improved 85C30 style
• Serial ports are USARTs
– Synchronous capability up to 1 Mbps, and include
HDLC/SDLC support
1999 Sep 24
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