XA-H4 Datasheet, PDF (37/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
1
ClkOut
t_CHAV
A
2
3
t_CHAH
RAS
ADDR
RAS
CASL
t_CHSL
t_AVSL
t_CHSL
t_AVSL
4
5
6
7
8
9
CAS ADDR
Even
CAS ADDR
ODD
t_CHSH
t_CPWH
OE
D[7:0]
t_DIS
LS Byte
t_DIH
Note 2
MS Byte
10
11
12
13
14
15
CAS ADDR
Even
CAS ADDR
ODD
t_CHSH
t_CHSH
Note 2
LS Byte
t_DIH
MS Byte
t_OHDE
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 9, 12, and 15 in this example).
Figure 18. DRAM FPM (Fast Page Mode) Burst Code Fetch on 8-Bit Bus
SU01285
1
2
3
4
5
ClkOut
t_CHAV
A
RAS
CASL
t_CHAH
RAS ADDRESS
t_CHSL
t_AVSL
CAS ADDR
EVEN
t_CHSH
t_CHSL
t_AVSL
6
7
8
CAS ADDR
ODD
CAS ADDR
EVEN
t_CPWL
t_CPWH
OE
Note 3
D[7:0]
t_DIS
LS Byte
Note 4
MS Byte
9
10
11
12
CAS ADDR
ODD
t_CHSH
LS Byte
t_CHSH
Note 4
MS Byte
t_OHDE
Note.
4-Byte Fetch is shown on 8-bit bus, burst can be 2 to 16 bytes.
To meet Hold Time, EDO DRAM drives Data until OE rises, or until a new falling edge of CAS.
Data bus is sampled on the rising edge of clock 6, and every three clocks thereafter (clocks 6, 8, 10, and 12 in this example).
Figure 19. EDO DRAM Burst Code Fetch on 8-Bit Bus
SU01286
1999 Sep 24
37