XA-H4 Datasheet, PDF (30/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
AC ELECTRICAL CHARACTERISTICS (3.3 V +/–10%)
V_DD = 3.3 V +/– 10%; T_amb = –40°C to +85°C (industrial)
Symbol
Figure
Parameter
Limits
Unit
Min
Max
All Cycles
F_C
t_C
t_CHCX
t_CLCX
t_CLCH
t_CHCL
t_AVSL
t_CHAH
t_CHAV
t_CHSH
t_CHSL
t_CODH
t_CPWH
t_CPWL
t_RP
23
23
23
23
23
All
All
All
All
All
24
11, 12, 17, 18, 19, 20
11, 19
22
System Clock (internally called CClk) Frequency
System Clock Period = 1/FC
XTALIN High Time
XTALIN Low Time
XTALIN Rise Time
XTALIN Fall Time
Address Valid to Strobe low
Address hold after ClkOut rising edge ⁹
Delay from ClkOut rising edge to address valid
Delay from ClkOut rising edge to Strobe High ⁹
Delay from ClkOut rising edge to Strobe Low ⁹
ClkOut Duty Cycle High (into 40 pF max.)
CAS Pulse Width High
CAS Pulse Width Low
All DRAM Cycles
RAS precharge time, thus minimum RAS high time⁸
Data Read Only
0
33.33
t_C* 0.5
t_C* 0.4
–
–
t_C – 21
1
–
1
1
t_CHCX–7
t_C – 12
t_C – 10
30
–
–
–
5
5
–
–
30
28
25
t_CHCX+3
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(n * t_C) – 16⁸
–
ns
t_AHDR
7, 14
Address hold (A19 – A1 only, not A0) after CS, BLE, BHE rise at
end of Data Read Cycle (not code fetch)
t_C – 12
–
ns
Data Read and Instruction Fetch Cycles
t_DIS
t_DIH
t_OHDE
7, 8, 10, 11, 12, 14, 15,
17, 18, 19
7, 8, 10, 14, 15, 17, 18
8, 10, 11, 14, 18
Data In Valid setup to ClkOut rising edge
Data In Valid hold after ClkOut rising edge ²
OE high to XA Data Bus Driver Enable
Write Cycles
32
0
t_C – 19
–
ns
–
ns
–
ns
t_CHDV
t_DVSL
t_SHAH
t_SHDH
9, 13
16, 20
9, 16
9, 16
Clock High to Data Valid
Data Valid prior to Strobe Low
Minimum Address Hold Time after strobe goes inactive
Data hold after strobes (CS and BHE/BLE) high
Refresh
–
t_C – 23
t_C – 25
t_C – 25
30
ns
–
ns
–
ns
–
ns
t_CLRL
21
CAS low to RAS low
Wait Input
t_C – 15
–
ns
t_WS
25
WAIT setup (stable high or low) prior to ClkOut rising edge
25
–
ns
t_WH
25
WAIT hold (stable high or low) after ClkOut rising edge
0
–
ns
NOTE:
1. On a 16-bit bus, if only one byte is being written, then only one of BLE_CASL or BHE_CASH will go active. On an 8-bit bus, BLE_CASL
goes active for all (odd or even address) accesses. BHE_CASH will not go active during any accesses on an 8-bit bus.
2. The bus timing is designed to make meeting hold time very straightforward without glue logic. On all generic reads and fetches, in order to
meet hold time, the slave should hold data valid on the bus until the earliest of CS, BHE/BLE, OE, goes high (inactive), or until the address
changes. On all FPM DRAM reads and fetches, hold data valid on the bus until a new CAS is asserted, or until OE goes high (inactive).
3. To avoid 3-State fights during read cycles and fetch cycles, do not drive data bus until OE goes active.
4. To meet hold time, EDO DRAM drives data onto the bus until OE rises, or until a new falling edge of CAS.
5. WARNING: ClkOut is specified at 40 pF max. More than 40 pf on ClkOut may significantly degrade the ClkOut waveform. Load
capacitance for all outputs (except ClkOut) = 80 pF.
6. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA-H4 User Manual for details.
7. When code is being fetched on the external bus, a burst mode fetch is used. This burst can be from 2 to 16 bytes long. On a 16-bit bus,
A3 – A1 are incremented for each new word of the burst. On an 8-bit bus, A3 – A0 are incremented for each new byte of the burst code fetch.
1999 Sep 24
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