XA-H4 Datasheet, PDF (35/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
ClkOut
A19 – A1
A0
CS
BLE
OE
D7 – D0
t_AVSL
t_CHSL
Driven by XA
Note 3
t_DIS
t_CHAV
t_CHSH
t_AHDR
Note 2
t_DIS
t_DIH
Note 2
t_OHDE
Driven by XA
On all cycles on 8-bit bus, BHE remains high (inactive)
Note:
On the external bus, ALL XA-H4 reads are 16-bit reads. If the CPU instruction only specifies 8-bits, then the CPU uses the appropriate byte, and discards the
extra byte. Thus, “8-Bit Reads” and “16-Bit Reads” appear to be identical on the bus. On an 8-bit bus, this will appear as two consecutive 8-bit reads even
though the CPU will only use one of the two bytes.
WARNING: Some 8-bit I/O devices (especially FIFOS) cannot operate correctly with 2 bytes being read for a one byte read. The most common (and least expensive)
solution is to operate these 8-bit devices on a 16-bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this tech-
nique is that byte reads are faster than on an 8-bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
Figure 14. Generic (SRAM, Flash, I/O Device, etc.) Read (16-Bit or 8-Bit) on 8-Bit Bus
SU01283
Clkout
t_CHAV
OE, BLE, CS
D[7:0]
t_CHAV
t_CHAV
t_CHAV
Even Address
Address + 1
Address + 2
Address + 3
t_CHAV
Note 3
t_DIS
t_DIH
Note 2
LS Byte
t_DIS
t_DIH
Note 2
MS Byte
t_DIS
t_DIH
Note 2
LS Byte
t_CHSH
t_DIS
t_DIH
Note 2
MS Byte
Note:
BHE remains high (inactive) for all accesses on an 8-bit bus. A burst code fetch can be
from 1 to 8 words (1 word = 2 bytes), a 2 word fetch is shown here.
Figure 15. Burst Code Fetch on 8-Bit Bus, Generic Memory
SU01245
1999 Sep 24
35