XA-H4 Datasheet, PDF (3/42 Pages) NXP Semiconductors – Single-chip 16-bit microcontroller

Philips Semiconductors
Single-chip 16-bit microcontroller
Preliminary specification
XA-H4
Table 1. XA-H3 and XA-H4 features comparison
Feature
Maximum External Memory
(Harvard Memory Mode)
Maximum External Memory
(Unified Memory Mode)
Memory Controller supports both Harvard and Unified architectures
De-multiplexed Address/Data Bus
DRAM Controller
DMA Channels
Dynamic Bus Sizing
Dynamic Bus Timing
Programmable Chip Selects
General Purpose IO Pins
Potential Interrupt Pins
Interrupts (programmable priority)
Two Counter/Timers plus Watchdog
Baud Rate Generators¹
Serial Ports
Maximum Serial Data Rates
Match Characters
Hardware Autobaud
NOTE:
1. Can be used as additional counters if not needed as BRGs.
XA-H3
6 MB
6 MB
Yes
Yes
No
8
Yes
Yes
6
33
16
7 Standard SW
4 High Priority SW
9 Hardware Event
Yes
4
4 UARTs
asynch to 230.4 kbps (no sync)
No
No
XA-H4
32 MB
(16 MB Code, 16 MB Data)
16 MB
Yes
Yes
Yes
8
Yes
Yes
6
33
16
7 Standard SW
4 High Priority SW
9 Hardware Event
Yes
4
4 USARTs
asynch to 230.4 kbps
sync to 1 Mbps
4 async chars per USART
up to 230.4 kbps
ORDERING INFORMATION
ROMless Only
Temperature range °C and Package
H4 = PXAH40KFBE –40 to +85°C, 100-Pin Low Profile Quad Flat Package (LQFP)
NOTE
K=30 MHz, F = (–40 to +85), BE = LQFP
Freq (MHz)
30
Package Drawing Number
SOT407-1
1999 Sep 24
3