ASX340AT Datasheet, PDF (70/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Two-Wire Serial Bus Timing
Figure 49 and Table 48 describe the timing for the two-wire serial interface.
Figure 49: Two-Wire Serial Bus Timing Parameters
SDATA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
SCLK
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
tSU;STO
P
S
Table 48:
Two-Wire Serial Bus Characteristics
f_EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; T_A = 25°C
Standard Mode
Fast Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
SCLK Clock Frequency
Hold time (repeated) START condition.
f_SCL
0
100
0
400
KHz
After this period, the first clock pulse is
t_HD;STA
4.0
-
0.6
-
s
generated
LOW period of the SCLK clock
t_LOW
4.7
-
1.3
-
s
HIGH period of the SCLK clock
t_HIGH
4.0
-
0.6
-
s
Set-up time for a repeated START condition
t_SU;STA
4.7
-
0.6
-
s
Data hold time
t_HD;DAT
0⁴
3.45⁵
0⁶
0.9⁵
s
Data set-up time
t_SU;DAT
250
-
100⁶
-
ns
Rise time of both SDATA and SCLK signals
t_r
-
1000 20 + 0.1Cb⁷ 300
ns
Fall time of both SDATA and SCLK signals
t_f
-
300
20 +
300
ns
0.1Cb⁷
Set-up time for STOP condition
t_SU;STO
4.0
-
0.6
-
s
Bus free time between a STOP and START
t_BUF
4.7
-
1.3
-
s
condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
C_b
-
400
-
400
pF
C_{IN_SI}
-
3.3
-
3.3
pF
C_{LOAD_SD}
-
30
-
30
pF
R_SD
1.5
4.7
1.5
4.7
K
Notes:
1. This table is based on I²C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I²C-compatible.
3. All values referred to V_IHmin = 0.9 VDD and V_ILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum t_HD;DAT has only to be met if the device does not stretch the LOW period (t_LOW) of
the SCLK signal.
6. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement
t_SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
ASX340AT/D Rev. H, 8/15 EN
70
©Semiconductor Components Industries, LLC, 2015.