ASX340AT Datasheet, PDF (10/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Descriptions and Assignments
Table 4:
Pin Descriptions
Pin Number
A2
B1
D2
E1
F1
F2
E2
D4
E4
H3
H2
F7
G7
E6
F8, D6, D7,
C6, C7, B6,
B7, A6
B3
C2
Pin Name
EXTCLK
XTAL
RESET_BAR
FRAME_SYNC
SCLK
SDATA
SADDR
SPI_SCLK
SPI_SDI
SPI_SDO
SPI_CS_N
FRAME_VALID
LINE_VALID
PIXCLK
DOUT[7:0]
DOUT_LSB1
DOUT_LSB0
Type
Description
Input
Output
Input
Input
Clock and Reset
Master input clock (27MHz): This can either be a square-wave generated from an
oscillator (in which case the XTAL input must be left unconnected) or connected
directly to a crystal.
If EXTCLK is connected to one pin of a crystal, this signal is connected to the other
pin; otherwise this signal must be left unconnected.
Asynchronous active-low reset: When asserted, the device will return all interfaces
to their reset state. When released, the device will initiate the boot sequence. This
signal has an internal pull-up resistor.
This input can be used to set the output timing of the ASX340AT to a fixed point in
the frame.
The input buffer associated with this input is permanently enabled. This signal
must be connected to GND if not used.
Register Interface
Input
These two signals implement the serial communications protocol for access to the
Input/Output ^{internal registers and variables.}
Input
This signal controls the device ID that will respond to serial communication
commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
Output
Input
Output
Output
SPI Interface
Clock output for interfacing to an external SPI memory such as Flash/EEPROM.
Tri-state when RESET_BAR is asserted.
Data in from SPI device. This signal has an internal pull-up resistor.
Data out to SPI device. Tri-state when RESET_BAR is asserted.
Chip selects to SPI device. Tri-state when RESET_BAR is asserted.
(Parallel) Pixel Data Output
Input/Output Pixel data from the ASX340AT can be routed out on this interface and processed
Input/Output ^externally.
Output
Output
To save power, these signals are driven to a constant logic level unless the parallel
pixel data output or alternate (GPIO) function is enabled for these pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose input/outputs.
Input/Output
Input/Output
When the sensor core is running in bypass mode, it will generate 10 bits of output
data per pixel. These two pins make the two LSB of pixel data available externally.
Leave DOUT_LSB1and DOUT_LSB0 unconnected if not used. To save power, these
signals are driven to a constant logic level unless the sensor core is running in
bypass mode or the alternate function is enabled for these pins. The slew rate of
these outputs is programmable.
ASX340AT/D Rev. H, 8/15 EN
10
©Semiconductor Components Industries, LLC, 2015.