ASX340AT Datasheet, PDF (60/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

Figure 40: Power Down Sequence
VDD (1.8)
VDD_IO (2.8)
VAA_PIX
VAA (2.8)
VDD_PLL
VDD_DAC (2.8)
EXTCLK
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
t0
t1
t2
t3
Power Down until next Power Up Cycle
Table 33: Power Down Sequence
Definition
VDD to VDD_IO
VDD_IO to VAA/VAA_PIX
VAA/VAA_PIX to VDD_PLL/DAC
Power Down until Next Power Up Time
Symbol
t0
t1
t2
t3
Minimum
0
0
0
100¹
Typical
–
–
–
–
Maximum
Unit
–
s
–
s
–
s
–
ms
(1) t3 is required between power down and next power up time, all decoupling caps from
regulators must completely discharge before next power up.
Figure 41: FRAME_SYNC to FRAME_VALID/LINE_VALID
t_{FRAME_SYNC}
FRAME_SYNC
FRAME_VALID
LINE_VALID
t_{FRMSYNH_FVH}
Table 34: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters
Parameter
Name
Conditions
Min
FRAME_SYNC to FV/LV
t_{FRMSYNC_FVH}
Interlaced mode
1.22
t_{FRAME_SYNC}
t_FRAMESYNC
1
Typ
Max
Unit
–
–
ms
s
ASX340AT/D Rev. H, 8/15 EN
60
©Semiconductor Components Industries, LLC, 2015.