ASX340AT Datasheet, PDF (56/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the ASX340AT launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 36.
As an option, the polarity of the PIXCLK can be inverted from the default by program-
ming R0x0016[14].
Figure 36: Digital Output I/O Timing
t
extclk_period
Input
EXTC LK
O utput
PIXC LK
O utput
D OUT [7:0]
O utput F R AM E_VALID
LIN E _VALID
t
pixclkf_dout
t
dout_ho
t
pixclkf_fvlv
t
dout_su
t
fvlv_su
t
fvlv_ho
Table 29:
Signal
EXTCLK
PIXCLK¹
DATA[7:0]
FV/LV
Parallel Digital Output I/O Timing
f_{EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;}
VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
Parameter
f_extclk
t_{extclk_period}
Duty cycle
f_pixclk
t_{pixclk_period}
Duty cycle
t_{pixclkf_dout}
t_{dout_su}
t_{dout_ho}
t_{pixclkf_fvlv}
t_{fvlv_su}
t_{fvlv_ho}
Conditions
Min
6
18.52
45
6
18.52
45
1.55
18
18
1.6
15
20
Typ
27
37
50
27
37.04
50
–
–
–
–
–
–
Max
54
166.67
55
54
166.67
55
1.9
20
20
3.05
16
21
Note: PIXCLK can be inverted from the default by programming R0x0016[14].
Unit
MHz
ns
%
MHz
ns
%
ns
ns
ns
ns
ns
ns
ASX340AT/D Rev. H, 8/15 EN
56
©Semiconductor Components Industries, LLC, 2015.