ASX340AT Datasheet, PDF (14/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
SOC Description
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable
gain and black offset, and timing and control as illustrated in Figure 4.
Figure 4: Sensor Core Block Diagram
Active Pixel
Sensor (APS)
Array
Control Register
Timing and Control
Communication
Bus
to IFP
Clock
Sync
Signals
Analog Processing
ADC
10-Bit Data
to IFP
Pixel Array Structure
The sensor core pixel array is configured as 728 columns by 560 rows, as shown in
Figure 5.
Figure 5: Pixel Array Description
(40, 36) (0, 0)
lens alignment rows
demosaic rows
Pixel logical address = (0, 0)
Active pixel array
640 x 480
Pixel logical address = (727, 559)
demosaic rows
lens alignment rows
(687, 523)
(not to scale)
Black rows used internally for automatic black level adjustment are not addressed by
default, but can be read out in raw output mode via a register setting.
There are 728 columns by 560 rows of optically-active pixels (that is, clear pixels) that
include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects
during color interpolation and correction. Among the 728 columns by 560 rows of clear
ASX340AT/D Rev. H, 8/15 EN
14
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