ASX340AT Datasheet, PDF (59/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

Figure 39: Power Up Sequence
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
VDD_PLL
VDD_DAC (2.8)
VAA_PIX
VAA (2.8)
VDD_IO (2.8)
VDD (1.8)
EXTCLK
RESET_BAR
t0
t1
t2
t3
Hard Reset
t4
Internal
Initialization
t5
Patch Config
SPI or Host
Streaming
Table 32: Power Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX
t0
0
–
–
s
VAA/VAA_PIX to VDD_IO
t1
0
–
–
s
VDD_IO to VDD
t2
0
–
–
s
Hard Reset
t3
2
–
–
s
Internal Initialization
t4
14
–
–
ms
Notes:
1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There
is no requirement on this from the sensor.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are
required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is
performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.
3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.
ASX340AT/D Rev. H, 8/15 EN
59
©Semiconductor Components Industries, LLC, 2015.