ASX340AT Datasheet, PDF (52/75 Pages) ON Semiconductor – Color CMOS NTSC/PAL Digital Image

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Reset and Clocks
Reset
Clocks
Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.
In the reset state, all control registers are set to default values. See “Device Configura-
tion” on page 28 for more details on Auto, Host, and Flash configurations.
Soft reset is asserted or de-asserted by the two-wire serial interface. In soft-reset mode,
the two-wire serial interface and the register bus are still running. All control registers
are reset using default values.
The ASX340AT has two primary clocks:
• A master clock coming from the EXTCLK signal.
• In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass
mode, PIXCLK runs at the same frequency as EXTCLK.
When the ASX340AT operates in raw Bayer bypass mode, the image flow pipeline clocks
can be shut off to conserve power.
The sensor core is a master in the system. The sensor core frame rate defines the overall
image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced
by the sensor configuration, and are also a function of certain image flow pipeline func-
tions. The relationship of the primary clocks is depicted in Figure 32.
The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr
or 565RGB—but has only an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.
Figure 32: Primary Clock Relationships
EXTCLK
Sensor
Master Clock
Sensor
Pixel Clock
Sensor Core
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
ASX340AT/D Rev. H, 8/15 EN
52
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