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AR0833 Datasheet, PDF (50/64 Pages) ON Semiconductor – 8 Mp CMOS Digital Image Sensor
AR0833: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor
Integration Time for Interlaced HDR Readout
When the flash_count = 0x3FF, the flash signal will be maximized and goes LOW when
readout starts, as shown in Figure 38 on page 50. This would be preferred if the latency in
closing the shutter is longer than the latency for turning off the flash. This guarantees
that the flash stays on while the shutter is open.
Figure 38: Extending FLASH Duration in Global Reset (Reference Readout Start)
Trigger
ERS
Wait for end of
current row
ROW RESET
INTEGRATION
global_rst_end
global_read_ start
SHUTTER
global_ shutter_start
(fixed)
Automatic at end
of frame readout
READOUT
ERS
~2*line_length_pck
FLASH
External Control of Integration Time
If global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is trig-
gered, the end of the integration phase is controlled by the level of trigger (global_se-
q_trigger[0] or the associated GPI input). This allows the integration time to be
controlled directly by an input to the sensor.
This operation corresponds to the shutter “B” setting on a traditional camera, where “B”
originally stood for “Bulb” (the shutter setting used for synchronization with a magne-
sium foil flash bulb) and was later considered to stand for “Brief” (an exposure that was
longer than the shutter could automatically accommodate).
When the trigger is de-asserted to end integration, the integration phase is extended by a
further time given by global_read_start – global_shutter_start. Usually this means that
global_read_start should be set to global_shutter_start + 1.
The operation of this mode is shown in Figure 39 on page 51. The figure shows the global
reset sequence being triggered by the GPI2 input, but it could be triggered by any of the
GPI inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under
software control.
The integration time of the GRR sequence is defined as:
Integration
Time
=
g----l--o---b----a---l--_---s---c---a---l--e---------[---g---l--o---b----a---l--_----r--e---a----d---_---s---t--a---r---t---–-----g---l--o----b---a---l--_----s--h----u---t--t--e---r---_---s---t--a---r---t---–-----g---l--o---b----a---l--_---r---s---t--_---e---n----d---]
vt_pix_clk_freq_mhz
(EQ 14)
Where:
AR0833_DS Rev. H Pub. 4/15 EN
50
©Semiconductor Components Industries, LLC, 2015.