AR0833 Datasheet, PDF (27/64 Pages) ON Semiconductor – 8 Mp CMOS Digital Image Sensor

AR0833: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor
Clocking
The pixel frequency can be calculated in general as:
pixel
clock
mhz
=
-----------------------------------------------e---x--t--_---c---l-k---_---f--r--e---q---_---m----h---z-----^-----p---l--l--_---m----u---l--t-i--p---l--i-e---r----------------------------------------------
pre_pll_clk_div  vt_sys_clk_div  2  vt_pix_clk_div  row_speed[2:0]
(EQ 1)
The output clock frequency can be calculated as:
clk_op_freq_mhz = _{p----r--e---_---p---l-l--_---c---l-k---_---d---i--v----}-----o-e--p-x--_-t-_-s--yc---sl--k_--_-c--f-l-rk--e-_--q-d--_-i--vm----_^{h---z-o---}_{p----_-p-p--l-i-l-x_---_m---c--u-l-k-l-t-_-i--pd---li-iv--e---r}----r---o---w----_---s--p---e---e--d---[---1---0---:--8---]-
(EQ 2)
op_sys_clk_freq_mhz
=
--e---x--t--_---c---l-k---_---f--r--e---q---_---m----h---z-----^-----p---l--l--_---m----u---l--t-i--p---l--i-e---r-
pre_pll_clk_div  op_sys_clk_div
(EQ 3)
PLL Clocking
Clock Control
The PLL divisors should be programmed while the AR0833 is in the software standby
state. After programming the divisors, it is necessary to wait for the VCO lock time before
enabling the PLL. The PLL is enabled by entering the streaming state.
An external timer will need to delay the entrance of the streaming mode by 1 millisecond
so that the PLL can lock.
The effect of programming the PLL divisors while the AR0833 is in the streaming state is
undefined.
The AR0833 uses an aggressive clock-gating methodology to reduce power consump-
tion. The clocked logic is divided into a number of separate domains, each of which is
only clocked when required.
When the AR0833 enters a soft standby state, almost all of the internal clocks are
stopped. The only exception is that a small amount of logic is clocked so that the two-
wire serial interface continues to respond to read and write requests.
AR0833_DS Rev. H Pub. 4/15 EN
27
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