AR0833 Datasheet, PDF (37/64 Pages) ON Semiconductor – 8 Mp CMOS Digital Image Sensor

AR0833: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor
Integration Time for Interlaced HDR Readout
Programming Restrictions when Subsampling
When subsampling is enabled and the sensor is switched back and forth between full
resolution and subsampling, ON Semiconductor recommends that line_length_pck be
kept constant between the two modes. This allows the same integration times to be used
in each mode.
When subsampling is enabled, it may be necessary to adjust the x_addr_start, x_ad-
dr_end, y_addr_start, and y_addr_end settings: the values for these registers are required
to correspond with rows/columns that form part of the subsampling sequence. The
adjustment should be made in accordance with these rules:
x_skip_factor = (x_odd_inc + 1) / 2
y_skip_factor = (y_odd_inc + 1) / 2
• x_addr_start should be a multiple of x_skip_factor * 4
• (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor * 4
• (y_addr_end - y_addr_start + y_odd_inc) should be a multiple of y_skip_factor * 4
The number of columns/rows read out with subsampling can be found from the equa-
tion below:
• columns/rows = (addr_end - addr_start + odd_inc) / skip_factor
Table 11 shows the row or column address sequencing for normal and subsampled
readout. In the 2X skip case, there are two possible subsampling sequences (because the
subsampling sequence only reads half of the pixels) depending upon the alignment of
the start address. Similarly, there will be four possible subsampling sequences in the 4X
skip case (though only the first two are shown in Table 11).
Table 11:
Row Address Sequencing During Subsampling
odd_inc = 1 (Normal)
start = 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
odd_inc = 3 (2X Skip)
start = 0
0
1
4
5
8
9
12
13
odd_inc = 7 (4X Skip)
start = 0
0
1
8
9
AR0833_DS Rev. H Pub. 4/15 EN
37
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