AR0833 Datasheet, PDF (26/64 Pages) ON Semiconductor – 8 Mp CMOS Digital Image Sensor

AR0833: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor
Clocking
Clocking
Default setup gives a physical 73.2 MHz internal clock for an external input clock of 24
MHz.
The sensor contains a phase-locked loop (PLL) for timing generation and control. The
PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply
the prescaler output, and a set of dividers to generate the output clocks. The PLL struc-
ture is shown in Figure 15.
Figure 15: Clocking Configuration
row_speed (R0x3016[2:0])
PLL
vt_pix_clk_div (R0x300)
External input clock
ext _ clk _ freq _mhz
EXTCLK
Pre PLL
Divider
(n +1)
vt_sys_clk_div (R0x302)
PLL input clock
pll _ ip _ clk _ freq
PLL internal VCO
frequency
PLL
Multiplier
(m)
vt sys clk
Divider
op sys clk
Divider
pre_pll_clk_div (R0x304) _{pll _multiplier(R0x306)}
op_sys_clk_div (R0x30A)
vt pix
clk
Divider
op pix
clk
Divider
op_pix_clk_div (R0x308)
clk _ pixel
Divider
clk _ pixel
vt_ pix _clk
vt_ _sys _clk
op _ sys_clk
op _ pix _clk
clk _op
Divider
clk _op
row_speed(R0x3016[10:8])
Figure 15 shows the different clocks and the names of the registers that contain or are
used to control their values. The vt_pix_clk is divided by two to compensate for the fact
that the design has 2 digital data paths. This divider should always remain turned on.
AR0833 has 10-to-8 and 10-to-6 compression. The Framer IP packs two 6-bit pixels into
one 12-bit data and sends it to Physical Layer. The Framer takes the action to divide
word clock into half speed. The word clock should be divided by 6 from VCO at PLL in
order to match Physical Layer considering one data having 12 bit-clocks.
The usage of the output clocks is shown below:
• clk_pixel (vt_pix_clk / row_speed[2:0]) is used by the sensor core to readout and
control the timing of the pixel array. The sensor core produces one 10-bit pixel each
vt_pix_clk period. The line length (line_length_pck) is controlled in increments of the
clk_pixel period.
• clk_op (op_pix_clk / row_speed[10:8]) is used to load parallel pixel data from the
output FIFO (see Figure 40 on page 52) to the serializer. The output FIFO generates
one pixel each op_pix_clk period.
• op_sys_clk is used to generate the serial data stream on the output. The relationship
between this clock frequency and the op_pix_clk frequency is dependent upon the
output data format.
AR0833_DS Rev. H Pub. 4/15 EN
26
©Semiconductor Components Industries, LLC, 2015.