TDA8023 Datasheet, PDF (9/32 Pages) NXP Semiconductors – Low power IC card interface

NXP Semiconductors
TDA8023
Low power IC card interface
Within the I²C-bus specifications, a Standard mode (100 kHz clock rate) and a Fast-speed
mode (400 kHz clock rate) are defined. The TDA8023 operates in both Fast-speed and
Standard modes.
By definition, a device that sends a signal is called a transmitter and a device that receives
the signal is called a receiver. The device that controls the signal is called the master. The
devices that are controlled by the master are called slaves.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level, put
on the bus by the transmitter. The master generates an extra acknowledge-related clock
pulse. The slave receiver that is addressed is obliged to generate an acknowledge after
the reception of each byte.
The master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge-related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an end
of data to the slave transmitter by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event, the transmitter must leave the data line HIGH
to enable the master generation of the STOP condition.
8.3.4 Device addressing
Each TDA8023 has 2 different addresses, one for each of its two registers.
Two TDA8023s may be used in parallel due to the address selection pin SAD0. Pin SAD0
is externally hardwired to pin V_DD or pin GND. The voltage on pin SAD0 sets address bit
b2: HIGH sets bit b2 to logic 1, LOW resets b2 to logic 0.
Address bit b1 selects Register 0 or Register 1.
Address bit b0 defines Read or Write operation: 1 means Read, 0 means Write.
The addresses for the TDA8023 are shown in Table 4 and Table 5.
Table 4. Device addressing
b7
b6
b5
b4
b3
b2
b1
b0
0
1
0
0
0
SAD0
0/1
R/W
Table 5. I²C-bus addresses for write mode
Pin SAD0
Register 0
L
40h
H
44h
Register 1
42h
46h
TDA8023_1
Product data sheet
Rev. 01 — 16 July 2007
© NXP B.V. 2007. All rights reserved.
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