TDA8023 Datasheet, PDF (7/32 Pages) NXP Semiconductors – Low power IC card interface

NXP Semiconductors
TDA8023
Low power IC card interface
8.2.2 With external divider on pin PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 to GND and R2 to V_DD as
shown in Figure 1 and Figure 2), then the internal threshold voltages and the internal
hysteresis voltage are overridden by externally determined ones.
The voltage on pin PORADJ is:
V _PORADJ = -_R----₁--^R--₊--¹---_R----₂- × V _DD = k × V _DD
where
k = -_R----₁--^R--₊--¹---_R----₂--
The thresholds that are applied by the TDA8023 to this voltage V_PORADJ are:
V _{th(H)(PORADJ )} = V _bg(int) + ^V-----₂^h--^y---^s (rising)
V _{th(L)(PORADJ )} = V _bg(int) – ^V-----₂^h--^y---^s (falling)
where
V_bg(int) = 1.25 V (typ)
V_hys = 60 mV (typ)
The thresholds and hysteresis on V_DD can then be calculated from:
V _th(POR)H = ^V-----^t-^h---⁽--^H----⁾--⁽-_k^P----^O---^R---^A---^D----^J--⁾ = ^---^V-----^b--^g---⁽--ⁱ-ⁿ---^t-_k-⁾---⁺-----^V---------2h-----^y-----s--^- (rising)
V _th(POR)L = -^V----^t-^h---⁽--^L---⁾--⁽-^P-_k--^O----^R---^A---^D----^J--⁾ = ^---^V-----^b--^g---⁽--ⁱ-ⁿ---^t-_k-⁾---^–----^V---------2-^h----y-----s--^- (falling)
V _hys(POR) = ^V-----_k^h--^y---^s
The minimum threshold voltage V_th(POR)L should be chosen higher than 2 V.
Input PORADJ is biased internally with a pull-down current source of 4 µA which is cut
when the voltage on this pin exceeds 1 V. This ensures that after detection of the external
bridge during power-on, the input current on this pin does not cause inaccuracy of the
bridge voltage.
8.2.3 External capacitor on pin CDEL
The width of the POR pulse (t_W) is externally set by the value of the CDEL capacitor: the
typical value is 1 ms per 2 nF. Usually C_CDEL = 22 nF, therefore t_W = 10 ms (typ).
TDA8023_1
Product data sheet
Rev. 01 — 16 July 2007
© NXP B.V. 2007. All rights reserved.
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