TDA8023 Datasheet, PDF (13/32 Pages) NXP Semiconductors – Low power IC card interface

NXP Semiconductors
TDA8023
Low power IC card interface
• Doubler:
– If V_CC = 5 V and V_DD(DCDC) = 4 V to 5.8 V
– If V_CC = 3 V and V_DD(DCDC) < 4 V
• Tripler:
– If V_CC = 5 V and V_DD(DCDC) < 4 V
8.4.2 Inductive configuration
The external components are a diode, a coil of 6.8 µH and a capacitor of 4.7 µF (see
Figure 2). In this configuration the DC-to-DC converter acts as follows.
• If V_CC = 5 V then V_VUP is regulated at 5.5 V
• If V_CC = 3 V then V_VUP is regulated at 4 V
• If V_CC = 1.8 V then the DC-to-DC converter acts as a follower
8.5 V_CC buffer
In all modes (follower, doubler, tripler), the DC-to-DC converter is able to deliver 60 mA
over the whole V_DD range (2.7 V to 6.5 V) or 90 mA if V_DD > 3 V.
The current on the V_CC buffer has an internal limitation of around 90 mA. When this limit is
reached, an automatic deactivation sequence is performed.
The V_CC voltage should be decoupled with a low-ESR capacitor between 100 nF and
168 nF. If the card socket is not very close to the TDA8023, one capacitor should be
placed near the TDA8023, and a second one near the card contacts.
8.6 Sequencer and clock counter
The sequencer takes care of ensuring activation and deactivation sequences according to
ISO 7816 and EMV 2000, even in case of emergency (card removal during transaction,
supply dropout or hardware problem).
The sequencer is clocked with an internal oscillator.
The activation of a card is initiated by setting bit START in the Command register, which is
only possible if the card is present and if the voltage supervisor is not active. The
activation sequence is described in Section 8.6.1.
The deactivation is initiated either by the system controller or automatically in case of a
hardware problem or a supply dropout. The deactivation sequence is described in
Section 8.6.2.
Outside a session, card contacts are forced low-impedance with respect to pin GNDC.
8.6.1 Activation sequence
When the card is inactive, pins V_CC, CLK, RST and I/O are LOW, which is low-impedance
with respect to pin GNDC. The DC-to-DC converter is stopped.
TDA8023_1
Product data sheet
Rev. 01 — 16 July 2007
© NXP B.V. 2007. All rights reserved.
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