TDA8023 Datasheet, PDF (15/32 Pages) NXP Semiconductors – Low power IC card interface

NXP Semiconductors
TDA8023
Low power IC card interface
8.6.2 Deactivation sequence
When the session is completed, the microcontroller resets bit START to logic 0 (t₁₀, see
Figure 6). The circuit then executes an automatic deactivation sequence:
1. Card reset: pin RST falls to LOW (t₁₁).
2. CLK is stopped (t₁₂).
3. Pin I/O falls to 0 V (t₁₃).
4. Pin V_CC falls to 0 V with a controlled slew rate (t₁₄).
5. The DC-to-DC converter is stopped and pins CLK, RST, V_CC and I/O become
low-impedance with relation to GNDC (t₁₅).
6. The internal oscillator changes to its low frequency (t₁₅).
t₁₁ = t₁₀ + ₆--^T--₄- , t₁₂ = t₁₁ + ^T-₂-- , t₁₃ = t₁₁ + T , t₁₄ = t₁₁ + ³---₂-^T-- and t₁₅ = t₁₁ + ⁷---₂-^T-- .
The deactivation time t_deact is the time that V_CC needs for going down to less than 0.4 V,
counted from the moment bit START is reset.
START
RST
CLK
I/O
V_CC
VUP
t₁₀ t₁₁
t₁₂
t₁₃
t₁₄
t₁₅
t_deact
Fig 6. Deactivation sequence
001aag619
8.7 Protection
All card contacts are protected against any short with any other card contact.
The currents on various pins are limited:
• on pin CLK: limited to ±70 mA
• on pin I/O: limited to ±10 mA (typical value)
• on pin RST: limited (only when this pin is LOW) to ±20 mA
• on pin V_CC: limited to 90 mA
If any of these currents exceeds its limit, an emergency deactivation sequence is
performed: pin INT is pulled LOW and bit PROT in the Status register is set.
TDA8023_1
Product data sheet
Rev. 01 — 16 July 2007
© NXP B.V. 2007. All rights reserved.
15 of 32