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TDA8023 Datasheet, PDF (12/32 Pages) NXP Semiconductors – Low power IC card interface
NXP Semiconductors
TDA8023
Low power IC card interface
Table 10. R1_01 - Register 1 subaddress 01 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0 D[7:0]
8-bit programmable CLK period count register;
range: 0 to 255;
initial value: 170
Table 11. R1_10 - Register 1 subaddress 10 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0 C[15:8]
8-bit programmable CLK period count register;
range in combination with C[7:0]: 0 to 65535;
initial value: 164
Table 12. R1_11 - Register 1 subaddress 11 in Read/Write mode bit description
Bit
Symbol
Description
7 to 0 C[7:0]
8-bit programmable CLK period count register;
range in combination with C[15:8]: 0 to 65535;
initial value: 116
If bit RSTIN = 0 when bit START is set to logic 1, then pin RST is controlled by bit RSTIN.
Else, pin RST = LOW during a number of CLK periods, defined by the 16-bit CLK count
register C[15:0], and goes HIGH afterwards.
There are two synchronous card management types:
• If bit PDWN = 0 when bit START is set to logic 1, then the output CLK is controlled by
input CLKIN (without division)
• If bit PDWN = 1 when bit START is set to logic 1, then the output CLK is controlled by
bit CLKPD1
8.4 DC-to-DC converter
For generating a supply voltage VCC of 5 V ± 5 % or 3 V ± 5 % to the card, an integrated
voltage converter is incorporated. This DC-to-DC converter should be separately supplied
by VDD(DCDC) on pin VDDP and GNDP (from 2.7 V to 6.5 V).
The DC-to-DC conversion is either capacitive or inductive, according to the external
components (automatic detection).
8.4.1 Capacitive configuration
The external components are three 100 nF capacitors (low-ESR), see Figure 1.
The DC-to-DC converter is either tripler, doubler or follower according to the respective
values of VCC and VDD(DCDC). An hysteresis of 100 mV is present on both thresholds:
• Follower:
– If VCC = 5 V and VDD(DCDC) > 5.8 V
– If VCC = 3 V and VDD(DCDC) > 4 V
– If VCC = 1.8 V
TDA8023_1
Product data sheet
Rev. 01 — 16 July 2007
© NXP B.V. 2007. All rights reserved.
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