NT3H2211W0FHKH Datasheet, PDF (64/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
11.3.2 NFC to I²C Data transfer
If the NFC interface is enabled (RF_LOCKED = 1b) and data is written to the terminator
page FFh of the SRAM via the NFC interface, at the end of the WRITE command, bit
SRAM_I2C_READY is set to 1b and bit RF_LOCKED is set to 0b automatically, and the
NTAG I²C plus is locked to the I²C interface.
To signal the host that data is ready to be read following mechanisms are in place:
• The host polls/reads bit SRAM_I2C_READY from NS_REG (see Table 14) to know if
data is ready in SRAM
• A trigger on the FD pin indicates to the host that data is ready to be read from SRAM.
This feature can be enabled by programming bits 5:2 (FD_OFF, FD_ON) of the
NC_REG appropriately (see Table 13)
This is illustrated in the Figure 29.
If the tag is addressed with the correct I²C slave address, the I2C_LOCKED bit is
automatically set to 1b (according to the interface arbitration). After a READ from the
terminator page of the SRAM, bit SRAM_I2C_READY and bit I2C_LOCKED are
automatically reset to 0b, and the tag returns to the arbitration idle mode where, for
example, further data from the NFC interface can be transferred.
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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